This invention relates to methods and systems for reducing heat flux in memory systems.
During the last two decades, DRAM technology has progressed dramatically. Device densities have increased from 1 Kbit per chip to 64 Mbits per chip, a factor of 64,000. DRAM performance has not kept pace with these density changes, since access times have decreased by about a factor of 5. Over the same 20 year period, microprocessor performance has jumped by several orders of magnitude. This growing disparity between the speed of microprocessors and that of DRAMs has forced system designers to create a variety of complicated and expensive hierarchical memory techniques, such as SRAM caches and parallel arrays of DRAMs. In addition, now that users demand high performance graphics, systems often rely on expensive frame buffers to provide the necessary bandwidth. And, due to the density increases in DRAMs, this need for bandwidth is required from fewer total chips.
To address this processor-to-memory performance gap, Rambus Inc., the assignee of this document, has developed a revolutionary chip-to-chip bus, termed the xe2x80x9cDirect Rambus Channelxe2x80x9d, that operates up to 10 times faster than conventional DRAMS. The Direct Rambus Channel connects memories to devices such as microprocessors, digital signal processors, graphics processors, and ASICs. The Channel uses a small number of very high speed signals to carry all address, data, and control information. Because it is able to transfer data at 1.6Gbytes per second at a moderate cost, the Direct Rambus Channel is ideal for high performance/low cost systems.
FIG. 1 shows an exemplary memory system generally at 10. System 10 typically includes a memory controller 12, one or more memory module boards 14 that support multiple DRAM devices 16 (or xe2x80x9cRDRAMsxe2x80x9d for xe2x80x9cRambus DRAMsxe2x80x9d). The memory controller 12 and the DRAM devices 16 are connected together by a high speed bus 18. The memory module(s) 14 is supported by a motherboard (not shown) that enables the high speed bus 18 to be routed to other memory modules that might be supported by the motherboard.
In order to allow lower power system operation, the RDRAM has several operating modes: Active, Standby, Nap, and Powerdown. The four modes are distinguished by two factors, their power consumption, and the time that it takes the RDRAM to execute a transaction from that mode.
In Active mode, the RDRAM is ready to immediately service a transaction. Power consumption is also higher in Active mode than in the other three modes. Unlike conventional DRAM memory systems, where each device in an entire bank of memory must consume Read/Write power through an entire access, Rambus memory systems use only one device to perform the Read or Write transfer, while the others revert to a lower power state. In the FIG. 1 example, only one of the RDRAMs 16 is ever actively reading or writing at one time.
Standby mode consumes less power than Active mode. Devices that are not involved in a transaction may be placed into a Standby mode by the memory controller to reduce power consumption. If an RDRAM is in Standby mode and is involved in a transaction, it must first transition to Active mode before it can service the transaction. An RDRAM may be instructed to transition to Standby mode at the end of a transaction.
Power consumption can be reduced by placing one or more RDRAMs into Nap mode. Nap mode uses less power than Standby mode, but it takes more time to transition to the Active mode from Nap mode than from Standby mode. Systems can achieve a large power savings by keeping the RDRAMs in Nap mode whenever they are not performing a Read or Write transaction. Power can further be reduced by placing one or more RDRAMs into Powerdown mode. Powerdown mode uses less power than Nap mode, but it takes more time to transition to the Active mode from Powerdown mode than from Nap mode.
An example of where these modes can be used is in a portable computer application. Here, power consumption can be reduced by placing a majority of the RDRAMs in Powerdown, while the RDRAM(s) that contain the frame buffer is placed in either Standby or Nap mode. This permits screen refresh to occur without powering up the entire memory system.
Because of the nature of the operation of the system described above (i.e. only one RDRAM is ever actively reading or writing at a particular instant in time), localized hot spots can develop on the memory module. It is desirable to dissipate this heat because of the adverse impact it can have on a memory system. Many techniques exist to dissipate heat including active techniques, such as the use of fans, and passive techniques such as the use of aluminum heat spreaders. As the push toward higher bandwidths continues, memory systems are going to have to be designed that not only meet the bandwidth requirements, but also operate well within desired tolerances are far as power dissipation and heat flux are concerned.
Accordingly, this invention arose out of concerns associated with providing improved methods and systems that provide high bandwidth memory systems with reduced heat flux.
Methods and systems for reducing heat flux in memory systems are described.
In one embodiment, a memory module comprises one or more faces and multiple channels on one or more of the faces. Multiple memory devices are disposed on each channel, with the memory devices being configured for operation in lock-step. Device IDs for each device are assigned and arranged so that power dissipation and hence heat flux per face is minimized.
In another embodiment, one or more memory modules each comprise one or more faces and multiple channels on one or more of the faces. Multiple DRAM devices arc disposed on each channel, with the DRAM devices being configured for operation in lock-step. Device IDs for each DRAM device are assigned, with corresponding DRAM devices on different channels having the same device ID. The device IDs are arranged so that no two DRAM devices have the same device ID on any one face.
In yet another embodiment, one or more memory modules each comprise one or more faces and multiple channels on one or more of the faces. Multiple DRAM devices are disposed on each channel, with the DRAM devices being configured for operation in lock-step. Device IDs are assigned for each DRAM device, with corresponding DRAM devices on different channels having the same device ID. The device IDs are arranged so that the physical distance between corresponding devices is maximized.
In a further embodiment, a memory module comprises one or more faces and multiple channels on one or more of the faces. Multiple memory devices are disposed on each channel, with the memory devices being configured for operation in lock-step. Device IDs are assigned for each memory device, with corresponding memory devices on different channels having the same device ID. There are enough memory devices so that at least one pair of corresponding devices have to appear on the same face of the module. Device IDs are arranged so that the physical distance between corresponding devices on a face is maximized.
In yet another embodiment, a memory module comprises front and back faces, and multiple devices on each face. A control line is provided and connects devices on each of the faces so that the connected devices commonly contribute multiple bits to a data bus.